The present invention relates to the transfer of data, for example the transmission of multiple data messages over a single transmission medium and the conversion of those messages into a form suitable for transmission.
There is a growing market in the field of digital communication. An increasing number of households have equipment to receive digital television, satellite and cable television, telephony and internet services. Telephony systems and the internet are interactive systems over which people can send and receive information and other digital communication systems are increasingly tending towards interactivity, for example as video-on-demand systems are introduced.
Video, audio and other information (e.g. internet services), all hereinafter referred lo as xe2x80x9cdataxe2x80x9d, can be transmitted along a number of transmission media, for example over electrical or optical cable or via radio. The data can be considered to be made up of xe2x80x9cmessagesxe2x80x9d, each message being, for example, one television channel or one internet connection. To allow a plurality of messages to be sent over a single transmission channel one approach is to split the messages into parts at the transmission device, transmit each part over the transmission channel and then recombine the parts at the receiving device to reconstitute the message. Each message is thus contained in a number of parts, which can arrive at the receiving device over a period of time. Additional information can be transmitted with each segment, for example to indicate the message of which the segment forms part. Consecutively sent messages need not then form part of the same message since the receiving device can use the additional information to allow it to recombine segments of each message with each other.
One system that uses this principle is AAL5. In this system data is transmitted in the form of asynchronous transfer mode (ATM) xe2x80x9ccellsxe2x80x9d of 53 bytes in length, of which the first 5 bytes constitute the additional information mentioned above and the other 48 bytes constitute the segment of the message. By convention each byte consists of 8 bits.
The messages themselves may be split into higher-level parts before they reach the transmission stage: for example video data can be in the form of MPEG frames.
One practical embodiment of a personal system for handling data in this form is a set-top box. This usually receives a digital data feed, forms the received data into digital messages, performs the necessary digital-to-analogue conversion and final backend processing of the messages and outputs signals suitable for use by other apparatus such as televisions, telephones or internet terminals. There is also normally provision for transmission of information (normally at a lower data rate) in the opposite direction to allow a user to operate interactive services. The reverse data can conveniently, although not necessarily be sent in the same format as the forward data.
In order to meet the demands of consumers for high data rate services such as video a set-top box should preferably be capable of receiving and transmitting at a rate of at least 1 to 10 Mbits/s and preferably of receiving at least 50 Mbits/s. This imposes very heavy demands on the processing systems that are to perform the transmitting and receiving operations, especially the segmentation of messages into parts and the reassembly of those parts. Since the set-top box is intended as a consumer product there is a particular need to provide a device for performing the transmitting and receiving operations that is as inexpensive as possible.
There are known integrated circuit systems that can perform the segmentation and re-assembly (xe2x80x9cSARxe2x80x9d) functions described above for use in a personal system. Current systems fall generally into two categories, having the following characteristics:
Hardware-based Designs
Very fast dedicated SAR engines (typically 155/622 Mbits/s)
Large silicon areas
Expensive, and although they are hardware-based systems they often still require a microprocessor for control purposes
Complicated control registers and memory management data structures defined in hardware
Inflexible, which makes it difficult to adapt them to rapidly evolving new standards and markets
Software/Processor-based Designs
Relatively slow (usually sub 20 Mbits/s)
Can be inexpensive with cheap RISC (reduced instruction set computing) processors, but become uneconomic in embedded situations at high data rates (40-50 Mbits/s upwards) because expensive high performance processors are needed
Flexible, as all control and data structures are software-defined, so easier to modify as standards evolve
In fact, there are four conflicting design requirements which need to be met for widespread consumer use:
Cost Targets. To a large extent the cost of an integrated circuit SAR engine is determined by the complexity of the circuit and the die area it occupies. Known hardware-based systems generally occupy large areas and whilst low-cost RISC software-based systems are cheaper to produce, their performance is modest.
Flexibility to meet evolving standards. Hardware-based systems are generally inflexible.
Performance targets. Existing hardware-based solutions have high performance but are too expensive for many consumer applications. Existing software-based solutions are cheaper but have modest performance.
Ease of Interfacing to other parts of the system
It is clear from the above analysis that the SAR engines currently available do not provide an effective technical and cost-effective solution.
According to a first aspect of the present invention there is provided a data stream transfer apparatus for receiving a data stream of data cells carrying real-time-sensitive information and transmitting data frames at predetermined time intervals, each data frame comprising data from one or more data cells, the apparatus comprising:
a receiving apparatus for receiving the data cells at variable time intervals and storing them in a buffer memory;.
a data transfer interface for transferring data frames out of the apparatus and, on transferring a data frame, generating an indication to a central processing unit of the apparatus; and
a memory access unit for receiving data defining a location in the buffer memory, accessing the buffer memory to retrieve a data frame from that location and transmitting that data frame to the data transfer interface;
wherein the central processing unit, upon receiving the indication from the data transfer interface, executes instructions to determine a time for transfer of a subsequent data frame, and on reaching that time transmits to the memory access unit the location of the subsequent frame in the buffer memory.
Preferably the apparatus is capable of receiving two or more streams of data cells, each data cell being received by the receiving apparatus with respective data stream indication data that indicates the data stream to which it relates, and wherein the receiving apparatus comprises means for storing the data cells from each stream in respective contiguous blocks in the buffer memory.
Preferably the receiving apparatus comprises:
a stream data memory for holding, for each data stream, stream data defining a location in the buffer memory, a position in the respective block and the length of the respective block;
a location memory for holding, for each data stream, an indication of the location of the stream data stored for that data stream in the stream data memory; and
loading apparatus for receiving the data cells and for each data cell accessing the location memory to determine the location of the stream data for the data stream to which the data cell relates, storing the cell in the buffer memory at the location indicated in the stream data, incrementing the stream data defining said location and said position for the block in the stream data memory by an amount equal to the length of the cell and comparing the incremented position with the stored length of a block for the data stream to determine whether the end of the block has been reached.
The central processing unit preferably has access to the stream data memory for storing the stream data.
Preferably the predetermined time intervals are substantially regular in interval and/or programmable and variable under software control.
Preferably the data frames are video data frames and/or MPEG frames and/or audio data frames. Each data frame preferably comprises data from AAL5 Protocol Data Units and/or data from ATM cells.
The data stream transfer apparatus is preferably provided on a single integrated circuit. The integrated circuit may include memory. At least part of the buffer memory is also preferably provided on the integrated circuit.
The memory access unit is preferably a hardware memory access unit and/or a direct memory access unit.
Preferably the indication to the central processing unit is an interrupt to the central processing unit.
According to a second aspect of the present invention there is provided a method for transmitting a plurality of data streams over a data channel, the method comprising performing the steps set out above in relation to the first aspect of the invention.